Crosstalk noise, such as capacitive crosstalk noise, continues to be a major concern for semiconductor integrated circuits (ICs). As the size, complexity, and operating or switching speeds of semiconductor ICs have increased while feature geometries have decreased, interconnect systems for such ICs have dramatically increased in complexity. In many situations this has increased the possible impact on timing due to noise resulting from parasitic capacitance within the interconnect system.
One approach that is used to analyze the impact of the parasitic capacitances is to model the interconnect system as an arrangement of nets (interconnections between gate outputs and interconnected gate inputs) inter coupled with parasitic capacitors. Static Timing Analysis (STA) is used to develop early and late arrival times (timing window) for each relevant net or node. This timing window is enlarged by a worst case assessment of crosstalk noise for both early and late arrival times using noise aware STA. This worst case timing window is used for timing analysis of all paths through the corresponding net and a list of paths that fail timing requirements are provided.
Designers of the IC then address the list of paths that fail timing analysis pursuant to resolving any timing issues. Unfortunately due to the pessimism, i.e. worst case approaches, of current noise aware STA many failed paths are found to be false failure indications and designer resources are needlessly wasted in addressing the false failures.